The invention relates to a device, to a precharge/homogenize circuit for a semiconductor device, and to a method for operating a semiconductor device.
With conventional semiconductor devices with a memory function, one differentiates, for instance, between functional memory devices (e.g., PLAs, PALs, etc.), and table memory devices, e.g., ROM devices (ROM=Read Only Memory, in one embodiment PROMs, EPROMs, EEPROMs, flash memories, etc.), and RAM devices (RAM=Random Access Memory or write-read memory, e.g., DRAMs and SRAMs), etc.
A RAM device is a memory for storing data under a predetermined address and for reading out the data again under this address later.
In the case of SRAMs (SRAM=Static Random Access Memory), the individual memory cells may, for instance, consist of few, for instance, 6 transistors, and in the case of DRAMs (DRAM=Dynamic Random Access Memory), for instance, of only one single, controlled capacitive element (e.g., the gate source capacitance of a MOSFET, or a capacitor, respectively) with the capacitance of which one respective bit can be stored as charge.
This charge, however, remains for a short time only. Therefore, a “refresh” must be performed regularly, e.g., approximately every 64 ms.
In contrast to this, no “refresh” has to be performed with SRAMs, i.e. the data stored in the memory cell remain stored as long as a supply voltage is fed to the SRAM.
In the case of non-volatile memory devices (NVMs), e.g., EPROMs, EEPROMs, and flash memories, the stored data, however, also remain stored if the supply voltage is switched off.
Furthermore, for a short time, “resistive” or “resistively switching” memory devices have been known, e.g., phase change memories or “PCMs”, etc.
In the case of RAMs, for instance, in one embodiment e.g., DRAMs, the respective memory cells/capacitors may be connected with bit lines that serve to transmit a data value that is to be read out from a memory cell, or a data value that is to be read into the memory cells.
On reading out a memory cell, an access transistor that is connected with the capacitor or the capacitive element of a memory cell can be connected through by the activation of a word line, and the charge state stored in the capacitor or the capacitive element can be applied to the bit line.
Then, a weak signal emanating from the capacitor or the capacitive element may be amplified by a read or write/sense amplifier. The read or write/sense amplifier may include complementary signal inputs. The bit lines connected with these signal inputs are referred to as bit line and complementary bit line.
With today's RAMs, in one embodiment DRAMs, “shared sense amplifiers” may be used as read or write/sense amplifiers so as to save chip space. In this case, a read or write/sense amplifier is used both during the reading out of a memory cell at the left side and of a memory cell at the right side along respective bit lines that are associated with a read or write/sense amplifier.
Prior to the reading out of the memory cells, the corresponding bit line sections, i.e. the corresponding sections of the non-complementary bit line and of the complementary bit line, may be precharged to the same potential by precharge/homogenize circuits that are connected with the bit lines. This potential may, for instance, correspond to half the voltage of a bit line in a logic high state (i.e., for instance, VBLH/2). This ensures that, prior to the reading out of data, no differences occur between the potential of the section of the bit line and the section of the complementary bit line, which could otherwise swap the small amount of charge that is transmitted to be bit lines by the capacitor or the capacitive element of a memory cell during the reading out. Directly prior to the reading out of the memory cells, the precharge/homogenize circuits that are connected with the bit line sections that are associated with the memory cell to be read out may be switched off.
Conventional precharge/homogenize circuits may, for instance, consist of three NMOS transistors each. The source drain path of a first one of the three NMOS transistors is connected between the bit line and the complementary bit line; the source drain paths of the two other NMOS transistors are connected in series, wherein the series connection is also connected between the bit line and the complementary bit line. The above-mentioned voltage VBLH/2 may be applied at the connection point of the source drain paths of the two NMOS transistors. The gates of the three NMOS-FETs are connected with each other and may be connected to a control voltage EQL that is supplied by a control circuit so as to switch the precharge/homogenize circuit on and off.
In one embodiment the relatively large path resistance to a NMOS transistor and the variable coupling of the precharge/homogenize circuit control voltage to the bit lines may, for instance, be of disadvantage with conventional precharge/homogenize circuits.